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Abstract

Accurate cycle-time forecasting remains a persistent challenge in semiconductor wafer fabrication due to highly dynamic, multivariate process conditions. This study proposes an optimized Hierarchical Transfer Learning with Hyperparameter Optimization (HTL-HPO) framework that integrates cross-fab knowledge transfer with Bayesian Tree-Structured Parzen Estimator–based optimization to improve predictive precision and generalization. The methodology involves hierarchical pretraining on source fabs, Maximum-Mean-Discrepancy–driven domain alignment, and probabilistic hyperparameter tuning for fine-grained adaptation to target lines. Using a real industrial multivariate dataset, the model’s performance was benchmarked against established baselines—Decision Tree, GRU, and LSTM—under consistent experimental protocols. The proposed approach achieved the lowest forecasting error (MSE = 0.006; RMSE = 0.079) and the highest explanatory power (R² = 0.934; Explained Variance = 0.938), with paired t-tests (p < 0.05) confirming statistically significant gains. Results reveal that hierarchical knowledge reuse and Bayesian optimization jointly enhance model stability, convergence speed, and robustness under noise and domain shifts. The findings underscore substantial operational implications for predictive scheduling, resource allocation, and sustainable production within smart-fab ecosystems. Overall, HTL-HPO offers a scalable, interpretable, and deployment-ready framework for next-generation intelligent manufacturing.

Keywords

Cycle-time forecasting Semiconductor manufacturing Hierarchical transfer learning Bayesian optimization Intelligent manufacturing

Article Details

How to Cite
Kumar, K. A. ., & Hemachandran , K. (2025). Optimized cycle time forecasting in semiconductor wafer fabrication via hierarchical transfer learning and hyperparameter optimization. Future Technology, 5(1), 55–64. Retrieved from https://fupubco.com/futech/article/view/534
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