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Abstract

Image compression is a basic need for efficient storage and transmission of high-resolution visual information of modern imaging and sensing systems. Algorithmic-level approximation within biorthogonal discrete wavelet transforms (DWT)-based compression has become an effective means in reducing the computation cost while keeping the image perceptual quality. A convolution-based wavelet framework introduced at the multiplier level to control the approximation leads to lower power usage and silicon area in hardware implementations in a systematic manner. In this work, the Multiplier Leadership Optimization Algorithm (MLOA) is used to select exact or approximate multiplier configurations under PSNR and SSIM constraints for energy-efficient hardware implementation. Wallace tree, Dadda tree, Vedic, and Baugh-Wooley multiplier architectures are embedded into the wavelet transform for efficient computation. Simulating with image datasets such as Castle, Baboon, Cameraman, Woman, and Boat shows that the evaluated configurations maintain PSNR values above 30 dB, while SSIM is used as the primary feasibility constraint for structurally sensitive images. The FPGA synthesis results show that Dadda-based MLOA configuration achieves the lowest normalized power and delay among the evaluated multiplier architectures,  while the Multiplier Leadership Optimization Algorithm-based Leader-Column Approximate Kogge-Stone Adder (MLOA-LC-AKSA) configuration achieves 145 LUTs, 3.6 ns delay, 52 mW power, 187.2 pJ power-delay product, and 277 MHz maximum frequency. Furthermore, the parallel execution of row-wise and column-wise wavelet convolutions yields a throughput improvement of up to 41%. These results validate the algorithmic-level approximation, HDL-based hardware feasibility, and the suggested framework's parallel-processing capacity as a scalable, energy-efficient, hardware-oriented high-resolution picture compression solution.  

Keywords

Image compression MLOA Approximate computing Discrete wavelet transform Parallel VLSI architecture

Article Details

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Anitha, R., & Sridevi, S. A. . (2026). Multiplier leadership optimization algorithm (MLOA) for high-resolution images in approximate DWT-based compression systems. Future Technology, 5(3), 175–191. Retrieved from https://fupubco.com/futech/article/view/965
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